Banks and the die

12.1 · Several banks work in parallel

A single giant array would be slow, because only one row can be open at a time. So a DRAM die divides its billions of cells into many independent banks, each its own array with its own row buffer. While one bank is busy opening a row or refreshing, another can be delivering data — overlapping work to hide delays and keep the shared data bus busy.

12.2 · Open-row buffer & chip data width

When a row is activated its whole contents sit latched in the sense amps as the open row. A later access to that same row is a fast ‘hit’; switching to a different row is a ‘miss’ that first costs extra cycles to precharge. Each chip also exposes only a modest data width — commonly x4, x8, or x16 bits per access — so no single chip fills the CPU’s bus alone; several are ganged together on the stick.