Flip-flop & SRAM cell

9.1 · Edge-triggered D flip-flop (master–slave)

A latch is ‘transparent’ — it changes whenever its enable is active, which is hard to coordinate across millions of cells. The flip-flop fixes this by capturing data only at the instant of a clock edge. An edge-triggered D flip-flop is two latches in a master–slave pair: the master grabs the input on one clock phase, the slave releases it on the next, so the bit updates cleanly once per tick. Chained together, flip-flops form registers, the fastest memory in a machine.

9.2 · The SRAM cell — six transistors per bit

Optimise this ‘hold a bit with feedback’ idea directly into silicon and you get the SRAM cell: two cross-coupled inverters (four transistors) holding the bit, plus two access transistors — six transistors per bit. SRAM is extremely fast and needs no refreshing while powered, which is exactly what CPU caches are made of. But six transistors per bit is bulky and expensive, so main memory takes a denser route.