The memory array (grid of cells)
11.1 · Cells laid out as a rows × columns grid
Section titled “11.1 · Cells laid out as a rows × columns grid”One cell holds one bit, so to store millions they are tiled into a two-dimensional array — a grid where each cell sits at the crossing of a horizontal word line (a row) and a vertical bit line (a column). This packs enormous numbers of bits into a tiny tile, and the row/column layout is what lets us reach any single cell.
11.2 · Addressing: RAS row, then CAS column
Section titled “11.2 · Addressing: RAS row, then CAS column”An address is split into a row part and a column part, delivered in two steps. First the Row Address Strobe (RAS) tells the row decoder to activate one whole word line, dumping that entire row into fast sense amplifiers that detect and restore the faint charges. Then the Column Address Strobe (CAS) picks which bit in that open row actually leaves the chip. Grouping cells this way is why memory naturally delivers 8, 16, 32 or 64 bits at once rather than one lonely bit.
